/* Date Stamp: 8/23/2014 */

#ifndef IIOCB_FUNC6_h
#define IIOCB_FUNC6_h

#include "DataTypes.h"

/* Device and Function specifications:                                        */
/* For all target CPUs:                                                       */
/* IIOCB_FUNC6_DEV 4                                                          */
/* IIOCB_FUNC6_FUN 6                                                          */

/* VID_IIOCB_FUNC6_REG supported on:                                          */
/*       IVT_EP (0x20026000)                                                  */
/*       IVT_EX (0x20026000)                                                  */
/*       HSX (0x20026000)                                                     */
/*       BDX (0x20026000)                                                     */
/* Register default value:              0x8086                                */
#define VID_IIOCB_FUNC6_REG 0x11062000
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x000
 */
typedef union {
  struct {
    UINT16 vendor_identification_number : 16;
    /* vendor_identification_number - Bits[15:0], RO, default = 16'b1000000010000110 
       The value is assigned by PCI-SIG to Intel.
     */
  } Bits;
  UINT16 Data;
} VID_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* DID_IIOCB_FUNC6_REG supported on:                                          */
/*       IVT_EP (0x20026002)                                                  */
/*       IVT_EX (0x20026002)                                                  */
/*       HSX (0x20026002)                                                     */
/*       BDX (0x20026002)                                                     */
/* Register default value on IVT_EP:    0x0E26                                */
/* Register default value on IVT_EX:    0x0E26                                */
/* Register default value on HSX:       0x2F26                                */
/* Register default value on BDX:       0x6F26                                */
#define DID_IIOCB_FUNC6_REG 0x11062002
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x002
 */
typedef union {
  struct {
    UINT16 device_identification_number : 16;
    /* device_identification_number - Bits[15:0], RO, default = 16'b0110111100100110 
       Device ID values vary from function to function. Bits 15:8 are equal to 0x6F for 
       BDX. The following 
       list is a breakdown of the function groups.0x6F00 - 0x6F1F : PCI Express and DMI 
       ports 
       0x6F20 - 0x6F3F : IO Features (Intel QuickData Technology, APIC, VT, RAS, Intel 
       TXT) 
       0x6F40 - 0x6F5F : Performance Monitors
       0x6F60 - 0x6F7F : DFX
       0x6F80 - 0x6F9F : Quick Path Interface
       0x6FA0 - 0x6FBF : Home Agent/Memory Controller
       0x6FC0 - 0x6FDF : Power Management
       0x6FE0 - 0x6FFF : Cbo/Ring
       Default value may vary based on bus, device, and function of this CSR location.
     */
  } Bits;
  UINT16 Data;
} DID_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* PCICMD_IIOCB_FUNC6_REG supported on:                                       */
/*       IVT_EP (0x20026004)                                                  */
/*       IVT_EX (0x20026004)                                                  */
/*       HSX (0x20026004)                                                     */
/*       BDX (0x20026004)                                                     */
/* Register default value:              0x0000                                */
#define PCICMD_IIOCB_FUNC6_REG 0x11062004
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x004
 */
typedef union {
  struct {
    UINT16 iose : 1;
    /* iose - Bits[0:0], RO, default = 1'b0 
       1
     */
    UINT16 mse : 1;
    /* mse - Bits[1:1], RW, default = 1'b0 
       1
     */
    UINT16 bme : 1;
    /* bme - Bits[2:2], RW, default = 1'b0 
       1
     */
    UINT16 sce : 1;
    /* sce - Bits[3:3], RO, default = 1'b0 
       1
     */
    UINT16 mwie : 1;
    /* mwie - Bits[4:4], RO, default = 1'b0 
       1
     */
    UINT16 vga_palette_snoop_enable : 1;
    /* vga_palette_snoop_enable - Bits[5:5], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 perre : 1;
    /* perre - Bits[6:6], RO, default = 1'b0 
       1
     */
    UINT16 idsel_stepping_wait_cycle_control : 1;
    /* idsel_stepping_wait_cycle_control - Bits[7:7], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 serre : 1;
    /* serre - Bits[8:8], RO, default = 1'b0 
       1
     */
    UINT16 fast_back_to_back_enable : 1;
    /* fast_back_to_back_enable - Bits[9:9], RO, default = 1'b0 
       Not applicable to PCI Express and is hardwired to 0
     */
    UINT16 intx_interrupt_disable : 1;
    /* intx_interrupt_disable - Bits[10:10], RW, default = 1'b0 
       1
     */
    UINT16 rsvd : 5;
    /* rsvd - Bits[15:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} PCICMD_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* PCISTS_IIOCB_FUNC6_REG supported on:                                       */
/*       IVT_EP (0x20026006)                                                  */
/*       IVT_EX (0x20026006)                                                  */
/*       HSX (0x20026006)                                                     */
/*       BDX (0x20026006)                                                     */
/* Register default value:              0x0010                                */
#define PCISTS_IIOCB_FUNC6_REG 0x11062006
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x006
 */
typedef union {
  struct {
    UINT16 rsvd_0 : 3;
    /* rsvd_0 - Bits[2:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 intxsts : 1;
    /* intxsts - Bits[3:3], RO_V, default = 1'b0 
       1
     */
    UINT16 capabilities_list : 1;
    /* capabilities_list - Bits[4:4], RO, default = 1'b1 
       This bit indicates the presence of a capabilities list structure
     */
    UINT16 pci66mhz_capable : 1;
    /* pci66mhz_capable - Bits[5:5], RO, default = 1'b0 
       Not applicable to PCI Express. Hardwired to 0.
     */
    UINT16 rsvd_6 : 1;
    /* rsvd_6 - Bits[6:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 fast_back_to_back : 1;
    /* fast_back_to_back - Bits[7:7], RO, default = 1'b0 
       Not applicable to PCI Express. Hardwired to 0.
     */
    UINT16 mdpe : 1;
    /* mdpe - Bits[8:8], RW1C, default = 1'b0 
       1
     */
    UINT16 devsel_timing : 2;
    /* devsel_timing - Bits[10:9], RO, default = 2'b00 
       Not applicable to PCI Express. Hardwired to 0.
     */
    UINT16 sta : 1;
    /* sta - Bits[11:11], RW1C, default = 1'b0 
       1
     */
    UINT16 rta : 1;
    /* rta - Bits[12:12], RO, default = 1'b0 
       1
     */
    UINT16 rma : 1;
    /* rma - Bits[13:13], RO, default = 1'b0 
       1
     */
    UINT16 sse : 1;
    /* sse - Bits[14:14], RO, default = 1'b0 
       1
     */
    UINT16 dpe : 1;
    /* dpe - Bits[15:15], RW1C, default = 1'b0 
       1
     */
  } Bits;
  UINT16 Data;
} PCISTS_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* RID_IIOCB_FUNC6_REG supported on:                                          */
/*       IVT_EP (0x10026008)                                                  */
/*       IVT_EX (0x10026008)                                                  */
/*       HSX (0x10026008)                                                     */
/*       BDX (0x10026008)                                                     */
/* Register default value:              0x00                                  */
#define RID_IIOCB_FUNC6_REG 0x11061008
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * "PCIe header Revision ID register"
 */
typedef union {
  struct {
    UINT8 revision_id : 8;
    /* revision_id - Bits[7:0], ROS_V, default = 8'b00000000 
       Reflects the Uncore Revision ID after reset.
       Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID 
       register in the processor uncore. 
       
     */
  } Bits;
  UINT8 Data;
} RID_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* CCR_N0_IIOCB_FUNC6_REG supported on:                                       */
/*       IVT_EP (0x10026009)                                                  */
/*       IVT_EX (0x10026009)                                                  */
/*       HSX (0x10026009)                                                     */
/*       BDX (0x10026009)                                                     */
/* Register default value:              0x00                                  */
#define CCR_N0_IIOCB_FUNC6_REG 0x11061009


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.4.6.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT8 register_level_programming_interface : 8;
    /* register_level_programming_interface - Bits[7:0], RO_V, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} CCR_N0_IIOCB_FUNC6_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CCR_N1_IIOCB_FUNC6_REG supported on:                                       */
/*       IVT_EP (0x2002600A)                                                  */
/*       IVT_EX (0x2002600A)                                                  */
/*       HSX (0x2002600A)                                                     */
/*       BDX (0x2002600A)                                                     */
/* Register default value:              0x0880                                */
#define CCR_N1_IIOCB_FUNC6_REG 0x1106200A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT16 sub_class : 8;
    /* sub_class - Bits[7:0], RO_V, default = 8'b10000000 
       The value changes dependent upon the dev/func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h80 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h01. 
                 dev-0x0 through 0x7 (return 0x4, d0f0 return 0x0 under default 
       settings) 
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
    UINT16 base_class : 8;
    /* base_class - Bits[15:8], RO_V, default = 8'b00001000 
       The value changes dependent upon the dev-func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h08 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h11. 
                 dev-0x0 through 0x7 (return 0x6)
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
  } Bits;
  UINT16 Data;
} CCR_N1_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* CLSR_IIOCB_FUNC6_REG supported on:                                         */
/*       IVT_EP (0x1002600C)                                                  */
/*       IVT_EX (0x1002600C)                                                  */
/*       HSX (0x1002600C)                                                     */
/*       BDX (0x1002600C)                                                     */
/* Register default value:              0x00                                  */
#define CLSR_IIOCB_FUNC6_REG 0x1106100C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x00c
 */
typedef union {
  struct {
    UINT8 cacheline_size : 8;
    /* cacheline_size - Bits[7:0], RW, default = 8'b00000000 
       This register is set as RW for compatibility reasons only. Cacheline size for 
       processor is always 64B. 
     */
  } Bits;
  UINT8 Data;
} CLSR_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* HDR_IIOCB_FUNC6_REG supported on:                                          */
/*       IVT_EP (0x1002600E)                                                  */
/*       IVT_EX (0x1002600E)                                                  */
/*       HSX (0x1002600E)                                                     */
/*       BDX (0x1002600E)                                                     */
/* Register default value:              0x80                                  */
#define HDR_IIOCB_FUNC6_REG 0x1106100E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x00e
 */
typedef union {
  struct {
    UINT8 configuration_layout : 7;
    /* configuration_layout - Bits[6:0], RO, default = 7'b0000000 
       This field identifies the format of the configuration header layout. It is Type 
       0 for all these devices. The default is 00h, indicating a 'endpoint device'. 
     */
    UINT8 multi_function_device : 1;
    /* multi_function_device - Bits[7:7], RO, default = 1'b1 
       This bit defaults to 1b since all these devices are multi-function
     */
  } Bits;
  UINT8 Data;
} HDR_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* CB_BAR_0_IIOCB_FUNC6_REG supported on:                                     */
/*       IVT_EP (0x40026010)                                                  */
/*       IVT_EX (0x40026010)                                                  */
/*       HSX (0x40026010)                                                     */
/*       BDX (0x40026010)                                                     */
/* Register default value:              0x00000004                            */
#define CB_BAR_0_IIOCB_FUNC6_REG 0x11064010
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x010
 */
typedef union {
  struct {
    UINT32 memory_space : 1;
    /* memory_space - Bits[0:0], RO, default = 1'b0  */
    UINT32 type : 2;
    /* type - Bits[2:1], RO, default = 2'b10  */
    UINT32 prefetchable : 1;
    /* prefetchable - Bits[3:3], RO, default = 1'b0  */
    UINT32 rsvd : 10;
    /* rsvd - Bits[13:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 bar : 18;
    /* bar - Bits[31:14], RW, default = 18'b000000000000000000  */
  } Bits;
  UINT32 Data;
} CB_BAR_0_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* CB_BAR_1_IIOCB_FUNC6_REG supported on:                                     */
/*       IVT_EP (0x40026014)                                                  */
/*       IVT_EX (0x40026014)                                                  */
/*       HSX (0x40026014)                                                     */
/*       BDX (0x40026014)                                                     */
/* Register default value:              0x00000000                            */
#define CB_BAR_1_IIOCB_FUNC6_REG 0x11064014
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x014
 */
typedef union {
  struct {
    UINT32 bar : 32;
    /* bar - Bits[31:0], RW, default = 32'b00000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} CB_BAR_1_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* SVID_IIOCB_FUNC6_REG supported on:                                         */
/*       IVT_EP (0x2002602C)                                                  */
/*       IVT_EX (0x2002602C)                                                  */
/*       HSX (0x2002602C)                                                     */
/*       BDX (0x2002602C)                                                     */
/* Register default value:              0x8086                                */
#define SVID_IIOCB_FUNC6_REG 0x1106202C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x02c
 */
typedef union {
  struct {
    UINT16 vendor_identification_number : 16;
    /* vendor_identification_number - Bits[15:0], RW_O, default = 16'b1000000010000110 
       1
     */
  } Bits;
  UINT16 Data;
} SVID_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* SDID_IIOCB_FUNC6_REG supported on:                                         */
/*       IVT_EP (0x2002602E)                                                  */
/*       IVT_EX (0x2002602E)                                                  */
/*       HSX (0x2002602E)                                                     */
/*       BDX (0x2002602E)                                                     */
/* Register default value:              0x0000                                */
#define SDID_IIOCB_FUNC6_REG 0x1106202E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x02e
 */
typedef union {
  struct {
    UINT16 subsystem_identification_number : 16;
    /* subsystem_identification_number - Bits[15:0], RW_O, default = 16'b0000000000000000 
       1
     */
  } Bits;
  UINT16 Data;
} SDID_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* CAPPTR_IIOCB_FUNC6_REG supported on:                                       */
/*       IVT_EP (0x10026034)                                                  */
/*       IVT_EX (0x10026034)                                                  */
/*       HSX (0x10026034)                                                     */
/*       BDX (0x10026034)                                                     */
/* Register default value:              0x80                                  */
#define CAPPTR_IIOCB_FUNC6_REG 0x11061034
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x034
 */
typedef union {
  struct {
    UINT8 capability_pointer : 8;
    /* capability_pointer - Bits[7:0], RO, default = 8'b10000000 
       Points to the first capability structure for the device which is the PCIe 
       capability. 
     */
  } Bits;
  UINT8 Data;
} CAPPTR_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* INTL_IIOCB_FUNC6_REG supported on:                                         */
/*       IVT_EP (0x1002603C)                                                  */
/*       IVT_EX (0x1002603C)                                                  */
/*       HSX (0x1002603C)                                                     */
/*       BDX (0x1002603C)                                                     */
/* Register default value:              0x00                                  */
#define INTL_IIOCB_FUNC6_REG 0x1106103C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x03c
 */
typedef union {
  struct {
    UINT8 interrupt_line : 8;
    /* interrupt_line - Bits[7:0], RW, default = 8'b00000000 
       N/A for these devices
     */
  } Bits;
  UINT8 Data;
} INTL_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* INTPIN_IIOCB_FUNC6_REG supported on:                                       */
/*       IVT_EP (0x1002603D)                                                  */
/*       IVT_EX (0x1002603D)                                                  */
/*       HSX (0x1002603D)                                                     */
/*       BDX (0x1002603D)                                                     */
/* Register default value:              0x03                                  */
#define INTPIN_IIOCB_FUNC6_REG 0x1106103D
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x03d
 */
typedef union {
  struct {
    UINT8 cb_intpin6 : 8;
    /* cb_intpin6 - Bits[7:0], RW_O, default = 8'b00000011 
       1
     */
  } Bits;
  UINT8 Data;
} INTPIN_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* MSIXCAPID_IIOCB_FUNC6_REG supported on:                                    */
/*       IVT_EP (0x10026080)                                                  */
/*       IVT_EX (0x10026080)                                                  */
/*       HSX (0x10026080)                                                     */
/*       BDX (0x10026080)                                                     */
/* Register default value:              0x11                                  */
#define MSIXCAPID_IIOCB_FUNC6_REG 0x11061080
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x080
 */
typedef union {
  struct {
    UINT8 cb_msixcapid : 8;
    /* cb_msixcapid - Bits[7:0], RO, default = 8'b00010001 
       1
     */
  } Bits;
  UINT8 Data;
} MSIXCAPID_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* MSIXNXTPTR_IIOCB_FUNC6_REG supported on:                                   */
/*       IVT_EP (0x10026081)                                                  */
/*       IVT_EX (0x10026081)                                                  */
/*       HSX (0x10026081)                                                     */
/*       BDX (0x10026081)                                                     */
/* Register default value:              0x90                                  */
#define MSIXNXTPTR_IIOCB_FUNC6_REG 0x11061081
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x081
 */
typedef union {
  struct {
    UINT8 cb_msixnxtptr : 8;
    /* cb_msixnxtptr - Bits[7:0], RO, default = 8'b10010000 
       1
     */
  } Bits;
  UINT8 Data;
} MSIXNXTPTR_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* MSIXMSGCTL_IIOCB_FUNC6_REG supported on:                                   */
/*       IVT_EP (0x20026082)                                                  */
/*       IVT_EX (0x20026082)                                                  */
/*       HSX (0x20026082)                                                     */
/*       BDX (0x20026082)                                                     */
/* Register default value:              0x0000                                */
#define MSIXMSGCTL_IIOCB_FUNC6_REG 0x11062082
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x082
 */
typedef union {
  struct {
    UINT16 table_size : 11;
    /* table_size - Bits[10:0], RO, default = 11'b00000000000 
       Indicates the MSI-X table size which for IIO is 1, encoded as a value of 0h.
     */
    UINT16 rsvd : 3;
    /* rsvd - Bits[13:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 function_mask : 1;
    /* function_mask - Bits[14:14], RW, default = 1'b0 
       If 1, the 1 vector associated with the dma is masked, regardless of the 
       per-vector mask bit state. If 0, the vector's mask bit determines whether the 
       vector is masked or not. Setting or clearing the MSI-X function mask bit has no 
       effect on the state of the per-vector Mask bit. 
     */
    UINT16 msi_x_enable : 1;
    /* msi_x_enable - Bits[15:15], RW, default = 1'b0 
       Software uses this bit to select between MSI-X or INTx method for signaling 
       interrupts from the DMA 
       0: INTx method is chosen for DMA interrupts
       1: MSI-X method is chosen for DMA interrupts
     */
  } Bits;
  UINT16 Data;
} MSIXMSGCTL_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* TABLEOFF_BIR_IIOCB_FUNC6_REG supported on:                                 */
/*       IVT_EP (0x40026084)                                                  */
/*       IVT_EX (0x40026084)                                                  */
/*       HSX (0x40026084)                                                     */
/*       BDX (0x40026084)                                                     */
/* Register default value:              0x00002000                            */
#define TABLEOFF_BIR_IIOCB_FUNC6_REG 0x11064084
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x084
 */
typedef union {
  struct {
    UINT32 table_bir : 3;
    /* table_bir - Bits[2:0], RO, default = 3'b000 
       Intel QuickData Technology DMA BAR is at offset 10h in the DMA config space and 
       hence this register is 0. 
     */
    UINT32 table_offset : 29;
    /* table_offset - Bits[31:3], RO, default = 29'b00000000000000000010000000000 
       MSI-X Table Structure is at offset 8K from the Intel QuickData Technology BAR 
       address. 
     */
  } Bits;
  UINT32 Data;
} TABLEOFF_BIR_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* PBAOFF_BIR_IIOCB_FUNC6_REG supported on:                                   */
/*       IVT_EP (0x40026088)                                                  */
/*       IVT_EX (0x40026088)                                                  */
/*       HSX (0x40026088)                                                     */
/*       BDX (0x40026088)                                                     */
/* Register default value:              0x00003000                            */
#define PBAOFF_BIR_IIOCB_FUNC6_REG 0x11064088
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x088
 */
typedef union {
  struct {
    UINT32 table_bir : 3;
    /* table_bir - Bits[2:0], RO, default = 3'b000 
       Intel QuickData Technology DMA BAR is at offset 10h in the DMA config space and 
       hence this register is 0. 
     */
    UINT32 table_offset : 29;
    /* table_offset - Bits[31:3], RO, default = 29'b00000000000000000011000000000 
       MSI-X PBA Structure is at offset 12K from the Intel QuickData Technology BAR 
       address. 
     */
  } Bits;
  UINT32 Data;
} PBAOFF_BIR_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* CAPID_IIOCB_FUNC6_REG supported on:                                        */
/*       IVT_EP (0x10026090)                                                  */
/*       IVT_EX (0x10026090)                                                  */
/*       HSX (0x10026090)                                                     */
/*       BDX (0x10026090)                                                     */
/* Register default value:              0x10                                  */
#define CAPID_IIOCB_FUNC6_REG 0x11061090
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * The PCI Express Capability List register enumerates the PCI Express Capability 
 * structure in the PCI 3.0 configuration space 
 */
typedef union {
  struct {
    UINT8 capability_id : 8;
    /* capability_id - Bits[7:0], RO, default = 8'b00010000 
       Provides the PCI Express capability ID assigned by PCI-SIG.
     */
  } Bits;
  UINT8 Data;
} CAPID_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* NEXTPTR_IIOCB_FUNC6_REG supported on:                                      */
/*       IVT_EP (0x10026091)                                                  */
/*       IVT_EX (0x10026091)                                                  */
/*       HSX (0x10026091)                                                     */
/*       BDX (0x10026091)                                                     */
/* Register default value:              0xE0                                  */
#define NEXTPTR_IIOCB_FUNC6_REG 0x11061091
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * The PCI Express Capability List register enumerates the PCI Express Capability 
 * structure in the PCI 3.0 configuration space 
 */
typedef union {
  struct {
    UINT8 next_ptr : 8;
    /* next_ptr - Bits[7:0], RO, default = 8'b11100000 
       This field is set to the PCI PM capability.
     */
  } Bits;
  UINT8 Data;
} NEXTPTR_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* EXPCAP_IIOCB_FUNC6_REG supported on:                                       */
/*       IVT_EP (0x20026092)                                                  */
/*       IVT_EX (0x20026092)                                                  */
/*       HSX (0x20026092)                                                     */
/*       BDX (0x20026092)                                                     */
/* Register default value:              0x0092                                */
#define EXPCAP_IIOCB_FUNC6_REG 0x11062092
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * The PCI Express Capabilities register identifies the PCI Express device type and 
 * associated capabilities 
 */
typedef union {
  struct {
    UINT16 capability_version : 4;
    /* capability_version - Bits[3:0], RO, default = 4'b0010 
       This field identifies the version of the PCI Express capability structure. Set 
       to 2h for PCI Express and DMA devices for compliance with the extended base 
       registers. 
     */
    UINT16 device_port_type : 4;
    /* device_port_type - Bits[7:4], RO, default = 4'b1001 
       This field identifies the type of device. It is set to for the DMA to indicate 
       root complex integrated endpoint device. 
     */
    UINT16 slot_implemented : 1;
    /* slot_implemented - Bits[8:8], RO, default = 1'b0 
       N/A
     */
    UINT16 interrupt_message_number : 5;
    /* interrupt_message_number - Bits[13:9], RO, default = 5'b00000 
       N/A
     */
    UINT16 rsvd : 2;
    /* rsvd - Bits[15:14], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} EXPCAP_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* DEVCAP_IIOCB_FUNC6_REG supported on:                                       */
/*       IVT_EP (0x40026094)                                                  */
/*       IVT_EX (0x40026094)                                                  */
/*       HSX (0x40026094)                                                     */
/*       BDX (0x40026094)                                                     */
/* Register default value:              0x00008000                            */
#define DEVCAP_IIOCB_FUNC6_REG 0x11064094
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * The PCI Express Device Capabilities register identifies device specific 
 * information for the device. 
 */
typedef union {
  struct {
    UINT32 max_payload_size : 3;
    /* max_payload_size - Bits[2:0], RO, default = 3'b000 
       Intel QuickData Technology DMA supports max 128B on writes to PCIExpress
     */
    UINT32 phantom_functions_supported : 2;
    /* phantom_functions_supported - Bits[4:3], RO, default = 2'b00 
       Intel QuickData Technology DMA does not support phantom functions.
     */
    UINT32 extended_tag_field_supported : 1;
    /* extended_tag_field_supported - Bits[5:5], RO, default = 1'b0  */
    UINT32 endpoint_l0s_acceptable_latency : 3;
    /* endpoint_l0s_acceptable_latency - Bits[8:6], RO, default = 3'b000 
       N/A
     */
    UINT32 endpoint_l1_acceptable_latency : 3;
    /* endpoint_l1_acceptable_latency - Bits[11:9], RO, default = 3'b000 
       N/A
     */
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[12:12], RO, default = 1'b0 
       Does not apply to Intel QuickData Technology DMA
     */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[13:13], RO, default = 1'b0 
       Does not apply to Intel QuickData Technology DMA
     */
    UINT32 power_indicator_present_on_device : 1;
    /* power_indicator_present_on_device - Bits[14:14], RO, default = 1'b0 
       Does not apply to Intel QuickData Technology DMA
     */
    UINT32 role_based_error_reporting : 1;
    /* role_based_error_reporting - Bits[15:15], RO, default = 1'b1 
       IIO is 1.1 compliant and so supports this feature
     */
    UINT32 rsvd_16 : 2;
    /* rsvd_16 - Bits[17:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 captured_slot_power_limit_value : 8;
    /* captured_slot_power_limit_value - Bits[25:18], RO, default = 8'b00000000 
       Does not apply to Intel QuickData Technology DMA
     */
    UINT32 captured_slot_power_limit_scale : 2;
    /* captured_slot_power_limit_scale - Bits[27:26], RO, default = 2'b00 
       Does not apply to Intel QuickData Technology DMA
     */
    UINT32 flr_supported : 1;
    /* flr_supported - Bits[28:28], RWS_O, default = 1'b0  */
    UINT32 rsvd_29 : 3;
    /* rsvd_29 - Bits[31:29], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DEVCAP_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* DEVCON_IIOCB_FUNC6_REG supported on:                                       */
/*       IVT_EP (0x20026098)                                                  */
/*       IVT_EX (0x20026098)                                                  */
/*       HSX (0x20026098)                                                     */
/*       BDX (0x20026098)                                                     */
/* Register default value:              0x0800                                */
#define DEVCON_IIOCB_FUNC6_REG 0x11062098
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * The PCI Express Device Control register controls PCI Express specific 
 * capabilities parameters associated with the device. 
 */
typedef union {
  struct {
    UINT16 correctable_error_reporting_enable : 1;
    /* correctable_error_reporting_enable - Bits[0:0], RO, default = 1'b0 
       N/A for Intel QuickData Technology DMA
     */
    UINT16 non_fatal_error_reporting_enable : 1;
    /* non_fatal_error_reporting_enable - Bits[1:1], RO, default = 1'b0 
       N/A for Intel QuickData Technology DMA
     */
    UINT16 fatal_error_reporting_enable : 1;
    /* fatal_error_reporting_enable - Bits[2:2], RO, default = 1'b0 
       N/A for Intel QuickData Technology DMA
     */
    UINT16 unsupported_request_reporting_enable : 1;
    /* unsupported_request_reporting_enable - Bits[3:3], RO, default = 1'b0 
       N/A for Intel QuickData Technology DMA
     */
    UINT16 enable_relaxed_ordering : 1;
    /* enable_relaxed_ordering - Bits[4:4], RW, default = 1'b0 
       For most parts, writes from Intel QuickData Technology DMA are relaxed ordered, 
       except for DMA completion writes. But the fact that Intel Quick Data Technology 
       DMA writes are relaxed ordered is not very useful except when the writes are 
       also non-snooped. If the writes are snooped, relaxed ordering does not provide 
       any particular advantage based on IIO uArch. But when writes are non-snooped, 
       relaxed ordering is required to get good BW and this bit is expected to be set. 
       If this bit is clear, NS writes will get very bad performance. 
     */
    UINT16 max_payload_size : 3;
    /* max_payload_size - Bits[7:5], RO, default = 3'b000 
       N/A for Intel QuickData Technology DMA
     */
    UINT16 extended_tag_field_enable : 1;
    /* extended_tag_field_enable - Bits[8:8], RO, default = 1'b0  */
    UINT16 phantom_functions_enable : 1;
    /* phantom_functions_enable - Bits[9:9], RO, default = 1'b0 
       Not applicable to Intel QuickData Technology DMA since it never uses phantom 
       functions as a requester. 
     */
    UINT16 auxiliary_power_management_enable : 1;
    /* auxiliary_power_management_enable - Bits[10:10], RO, default = 1'b0 
       Not applicable to Intel QuickData Technology DMA
     */
    UINT16 enable_no_snoop : 1;
    /* enable_no_snoop - Bits[11:11], RW, default = 1'b1 
       For Intel QuickData Technology DMA, when this bit is clear, all DMA transactions 
       must be snooped. When set, DMA transactions to main memory can utilize No Snoop 
       optimization under the guidance of the device driver. 
     */
    UINT16 max_read_request_size : 3;
    /* max_read_request_size - Bits[14:12], RO, default = 3'b000 
       N/A to Intel QuickData Technology DMA since it does not issue tx on PCIE
     */
    UINT16 initiate_flr : 1;
    /* initiate_flr - Bits[15:15], RW, default = 1'b0 
       Intel QuickData Technology DMA does a reset of that function only per the FLR 
       ECN. This bit always returns 0 when read and a write of 0 has no impact 
     */
  } Bits;
  UINT16 Data;
} DEVCON_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* DEVSTS_IIOCB_FUNC6_REG supported on:                                       */
/*       IVT_EP (0x2002609A)                                                  */
/*       IVT_EX (0x2002609A)                                                  */
/*       HSX (0x2002609A)                                                     */
/*       BDX (0x2002609A)                                                     */
/* Register default value:              0x0000                                */
#define DEVSTS_IIOCB_FUNC6_REG 0x1106209A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * The PCI Express Device Status register provides information about PCI Express 
 * device specific parameters associated with the device 
 */
typedef union {
  struct {
    UINT16 correctable_error_detected : 1;
    /* correctable_error_detected - Bits[0:0], RO, default = 1'b0 
       N/A for Intel QuickData Technology DMA
     */
    UINT16 non_fatal_error_detected : 1;
    /* non_fatal_error_detected - Bits[1:1], RO, default = 1'b0 
       N/A for Intel QuickData Technology DMA
     */
    UINT16 fatal_error_detected : 1;
    /* fatal_error_detected - Bits[2:2], RO, default = 1'b0 
       N/A for Intel QuickData Technology DMA
     */
    UINT16 unsupported_request_detected : 1;
    /* unsupported_request_detected - Bits[3:3], RO, default = 1'b0 
       N/A for Intel QuickData Technology DMA
     */
    UINT16 aux_power_detected : 1;
    /* aux_power_detected - Bits[4:4], RO, default = 1'b0 
       Does not apply to IIO
     */
    UINT16 transactions_pending : 1;
    /* transactions_pending - Bits[5:5], RO, default = 1'b0 
       1: indicates that the Intel QuickData Technology DMA device has outstanding 
       Non-Posted Request which it has issued either towards main memory, which have 
       not been completed. 0: Intel Quick Data Technology DMA reports this bit cleared 
       only when all Completions for any outstanding Non-Posted Requests it owns have 
       been received. 
     */
    UINT16 rsvd : 10;
    /* rsvd - Bits[15:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} DEVSTS_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* DEVCAP2_IIOCB_FUNC6_REG supported on:                                      */
/*       IVT_EP (0x400260B4)                                                  */
/*       IVT_EX (0x400260B4)                                                  */
/*       HSX (0x400260B4)                                                     */
/*       BDX (0x400260B4)                                                     */
/* Register default value:              0x00000010                            */
#define DEVCAP2_IIOCB_FUNC6_REG 0x110640B4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x0b4
 */
typedef union {
  struct {
    UINT32 completion_timeout_values_supported : 4;
    /* completion_timeout_values_supported - Bits[3:0], RO, default = 4'b0000 
       Not Supported
     */
    UINT32 completion_timeout_disable_supported : 1;
    /* completion_timeout_disable_supported - Bits[4:4], RO, default = 1'b1  */
    UINT32 rsvd : 27;
    /* rsvd - Bits[31:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DEVCAP2_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* DEVCON2_IIOCB_FUNC6_REG supported on:                                      */
/*       IVT_EP (0x200260B8)                                                  */
/*       IVT_EX (0x200260B8)                                                  */
/*       HSX (0x200260B8)                                                     */
/*       BDX (0x200260B8)                                                     */
/* Register default value:              0x0000                                */
#define DEVCON2_IIOCB_FUNC6_REG 0x110620B8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x0b8
 */
typedef union {
  struct {
    UINT16 completion_timeout_value : 4;
    /* completion_timeout_value - Bits[3:0], RO, default = 4'b0000  */
    UINT16 completion_timeout_disable : 1;
    /* completion_timeout_disable - Bits[4:4], RW, default = 1'b0  */
    UINT16 rsvd : 11;
    /* rsvd - Bits[15:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} DEVCON2_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* PMCAP_IIOCB_FUNC6_REG supported on:                                        */
/*       IVT_EP (0x400260E0)                                                  */
/*       IVT_EX (0x400260E0)                                                  */
/*       HSX (0x400260E0)                                                     */
/*       BDX (0x400260E0)                                                     */
/* Register default value:              0x00030001                            */
#define PMCAP_IIOCB_FUNC6_REG 0x110640E0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x0e0
 */
typedef union {
  struct {
    UINT32 capability_id : 8;
    /* capability_id - Bits[7:0], RO, default = 8'b00000001 
       Provides the PM capability ID assigned by PCI-SIG.
     */
    UINT32 next_capability_pointer : 8;
    /* next_capability_pointer - Bits[15:8], RO, default = 8'b00000000 
       This is the last capability in the chain and hence set to 0.
     */
    UINT32 version : 3;
    /* version - Bits[18:16], RWS_O, default = 3'b011 
       This field is set to 3h (PM 1.2 compliant) as version number. Bit is RW-O to 
       make the version 2h incase legacy OS'es have any issues. 
     */
    UINT32 pme_clock : 1;
    /* pme_clock - Bits[19:19], RO, default = 1'b0 
       This field is hardwired to 0h as it does not apply to PCI Express.
     */
    UINT32 rsvd : 1;
    /* rsvd - Bits[20:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 device_specific_initialization : 1;
    /* device_specific_initialization - Bits[21:21], RO, default = 1'b0  */
    UINT32 aux_current : 3;
    /* aux_current - Bits[24:22], RO, default = 3'b000  */
    UINT32 d1_support : 1;
    /* d1_support - Bits[25:25], RO, default = 1'b0 
       I/OxAPIC does not support power management state D1.
     */
    UINT32 d2_support : 1;
    /* d2_support - Bits[26:26], RO, default = 1'b0 
       I/OxAPIC does not support power management state D2.
     */
    UINT32 pme_support : 5;
    /* pme_support - Bits[31:27], RO, default = 5'b00000 
       Bits 31, 30 and 27 must be set to \q1\q for PCI-PCI bridge structures 
       representing ports on root complexes. 
     */
  } Bits;
  UINT32 Data;
} PMCAP_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* PMCSR_IIOCB_FUNC6_REG supported on:                                        */
/*       IVT_EP (0x400260E4)                                                  */
/*       IVT_EX (0x400260E4)                                                  */
/*       HSX (0x400260E4)                                                     */
/*       BDX (0x400260E4)                                                     */
/* Register default value:              0x00000008                            */
#define PMCSR_IIOCB_FUNC6_REG 0x110640E4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x0e4
 */
typedef union {
  struct {
    UINT32 power_state : 2;
    /* power_state - Bits[1:0], RW_V, default = 2'b00 
       This 2-bit field is used to determine the current power state of the function 
       and to set a new power state as well. 
       00: D0
       01: D1 (not supported by IOAPIC)
       10: D2 (not supported by IOAPIC)
       11: D3_hot
       If Software tries to write 01 or 10 to this field, the power state does not 
       change from the existing power state (which is either D0 or D3hot) and nor do 
       these bits1:0 change value. 
       When in D3hot state, I/OxAPIC will
       a) respond to only Type 0 configuration transactions targeted at the device's 
       configuration space, when in D3hot state 
       c) will not respond to memory (i.e. D3hot state is equivalent to MSE ), accesses 
       to MBAR region (note: ABAR region access still go through in D3hot state, if it 
       enabled) 
       d) will not generate any MSI writes
     */
    UINT32 rsvd_2 : 1;
    /* rsvd_2 - Bits[2:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 no_soft_reset : 1;
    /* no_soft_reset - Bits[3:3], RO, default = 1'b1 
       Indicates I/OxAPIC does not reset its registers when transitioning from D3hot to 
       D0. 
     */
    UINT32 rsvd_4 : 4;
    /* rsvd_4 - Bits[7:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pme_enable : 1;
    /* pme_enable - Bits[8:8], RO, default = 1'b0 
       Not relevant for I/OxAPIC
     */
    UINT32 data_select : 4;
    /* data_select - Bits[12:9], RO, default = 4'b0000 
       Not relevant for I/OxAPIC
     */
    UINT32 data_scale : 2;
    /* data_scale - Bits[14:13], RO, default = 2'b00 
       Not relevant for I/OxAPIC
     */
    UINT32 pme_status : 1;
    /* pme_status - Bits[15:15], RO, default = 1'b0 
       Not relevant for I/OxAPIC
     */
    UINT32 rsvd_16 : 6;
    /* rsvd_16 - Bits[21:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 b2_b3_support : 1;
    /* b2_b3_support - Bits[22:22], RO, default = 1'b0 
       Not relevant for I/OxAPIC
     */
    UINT32 bus_power_clock_control_enable : 1;
    /* bus_power_clock_control_enable - Bits[23:23], RO, default = 1'b0 
       Not relevant for I/OxAPIC
     */
    UINT32 data : 8;
    /* data - Bits[31:24], RO, default = 8'b00000000 
       Not relevant for I/OxAPIC
     */
  } Bits;
  UINT32 Data;
} PMCSR_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* CHANERR_INT_IIOCB_FUNC6_REG supported on:                                  */
/*       IVT_EP (0x40026180)                                                  */
/*       IVT_EX (0x40026180)                                                  */
/*       HSX (0x40026180)                                                     */
/*       BDX (0x40026180)                                                     */
/* Register default value:              0x00000000                            */
#define CHANERR_INT_IIOCB_FUNC6_REG 0x11064180
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x180
 */
typedef union {
  struct {
    UINT32 dma_trans_saddr_err : 1;
    /* dma_trans_saddr_err - Bits[0:0], RW1CS, default = 1'b0 
       DMA Transfer Source Address Error. The DMA channel sets this bit indicating that 
       the current descriptor has an illegal source address. When this bit has been 
       set, the address of the failure descriptor has been stored in the Channel Status 
       register. 
     */
    UINT32 dma_xfrer_daddr_err : 1;
    /* dma_xfrer_daddr_err - Bits[1:1], RW1CS, default = 1'b0 
       DMA Transfer Destination Address Error. The DMA channel sets this bit indicating 
       that the current descriptor has an illegal destination address. When this bit 
       has been set, the address of the failure descriptor has been stored in the 
       Channel Status register. 
     */
    UINT32 nxt_desc_addr_err : 1;
    /* nxt_desc_addr_err - Bits[2:2], RW1CS, default = 1'b0 
       Next Descriptor Address Error. The DMA channel sets this bit indicating that the 
       current descriptor has an illegal next descriptor address including an alignment 
       error (not on a 64-byte boundary). When this bit has been set and the channel 
       returns to the Halted state, the address of the failed descriptor is in the 
       Channel Status register. 
     */
    UINT32 descriptor_error : 1;
    /* descriptor_error - Bits[3:3], RW1CS, default = 1'b0 
       The DMA channel sets this bit indicating that the current transfer has 
       encountered an error (not otherwise covered under other error bits) when reading 
       or executing a DMA descriptor. When this bit has been set and the channel 
       returns to the Halted state, the address of the failed descriptor is in the 
       Channel Status register. 
     */
    UINT32 chn_addr_valerr : 1;
    /* chn_addr_valerr - Bits[4:4], RW1CS, default = 1'b0 
       Chain Address Value Error. The DMA channel sets this bit indicating that the 
       CHAINADDR register has an illegal address including an alignment error (not on a 
       64-byte boundary). 
     */
    UINT32 chancmd_err : 1;
    /* chancmd_err - Bits[5:5], RW1CS, default = 1'b0 
       CHANCMD Error. The DMA channel sets this bit indicating that a write to the 
       CHANCMD register contained an invalid value (e.g. more than one command bit 
       set). 
     */
    UINT32 cdata_parerr : 1;
    /* cdata_parerr - Bits[6:6], RW1CS, default = 1'b0 
       Data Parity Error. The DMA channel sets this bit indicating that the current 
       transfer has encountered a parity error. When this bit has been set, the address 
       of the failed descriptor is in the Channel Status register. 
     */
    UINT32 dma_data_parerr : 1;
    /* dma_data_parerr - Bits[7:7], RW1CS, default = 1'b0 
       DMA Data Parity Error. The DMA channel sets this bit indicating that the current 
       transfer has encountered an uncorrectable ECC/parity error reported by the DMA 
       engine. 
     */
    UINT32 rd_data_err : 1;
    /* rd_data_err - Bits[8:8], RW1CS, default = 1'b0 
       Read Data Error. The DMA channel sets this bit indicating that the current 
       transfer has encountered an error while accessing the source data. This error 
       could be a read data that is received poisoned. When this bit has been set, the 
       address of the failed descriptor is in the Channel Status register. 
     */
    UINT32 wr_data_err : 1;
    /* wr_data_err - Bits[9:9], RW1CS, default = 1'b0 
       Write Data Error. The DMA channel sets this bit indicating that the current 
       transfer has encountered an error while writing the destination data. This error 
       could be because of an internal ram error in the write queue that stores the 
       write data before being written to main memory. When this bit has been set, the 
       address of the failed descriptor is in the Channel Status register. 
     */
    UINT32 desc_ctrl_err : 1;
    /* desc_ctrl_err - Bits[10:10], RW1CS, default = 1'b0 
       Descriptor Control Error. The DMA channel sets this bit indicating that the 
       current transfer has an illegal control field value. When this bit has been set, 
       the address of the failed descriptor is in the Channel Status register. 
     */
    UINT32 desc_len_err : 1;
    /* desc_len_err - Bits[11:11], RW1CS, default = 1'b0 
       Descriptor Length Error. The DMA channel sets this bit indicating that the 
       current transfer has an illegal length field value. When this bit has been set, 
       the address of the failed descriptor is in the Channel Status register. 
     */
    UINT32 cmp_addr_err : 1;
    /* cmp_addr_err - Bits[12:12], RW1CS, default = 1'b0 
       Completion Address Error. The DMA channel sets this bit indicating that the 
       completion address register was configured to an illegal address or has not been 
       configured. 
     */
    UINT32 int_cfg_err : 1;
    /* int_cfg_err - Bits[13:13], RW1CS, default = 1'b0 
       Interrupt Configuration Error. The DMA channel sets this bit indicating that the 
       interrupt registers were not configured properly when the DMA channel attempted 
       to generate an interrupt e.g. interrupt address is not 0xFEE. 
     */
    UINT32 unused : 1;
    /* unused - Bits[14:14], RO, default = 1'b0  */
    UINT32 unaffil_err : 1;
    /* unaffil_err - Bits[15:15], RO, default = 1'b0 
       Unaffiliated Error. IIO never sets this bit
     */
    UINT32 crc_xorp_err : 1;
    /* crc_xorp_err - Bits[16:16], RW1CS, default = 1'b0 
       The hardware sets this bit when a CRC Test operation or XOR Validity operation 
       fails or when the P validation part of the XOR with Galois Field Multiply 
       Validate operation fails. 
     */
    UINT32 rsvd : 15;
    /* rsvd - Bits[31:17], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CHANERR_INT_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* CHANERRMSK_INT_IIOCB_FUNC6_REG supported on:                               */
/*       IVT_EP (0x40026184)                                                  */
/*       IVT_EX (0x40026184)                                                  */
/*       HSX (0x40026184)                                                     */
/*       BDX (0x40026184)                                                     */
/* Register default value:              0x00000000                            */
#define CHANERRMSK_INT_IIOCB_FUNC6_REG 0x11064184
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x184
 */
typedef union {
  struct {
    UINT32 mask13_0 : 14;
    /* mask13_0 - Bits[13:0], RWS, default = 14'b00000000000000 
       This register is a bit for bit mask for the CHANERR_INT register
       0: enable
       1: disable
     */
    UINT32 rsvd_14 : 1;
    /* rsvd_14 - Bits[14:14], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 chanerrintmskro : 1;
    /* chanerrintmskro - Bits[15:15], RO, default = 1'b0  */
    UINT32 mask16 : 1;
    /* mask16 - Bits[16:16], RWS, default = 1'b0 
       This register is a bit for bit mask for the CHANERR_INT register
       0: enable
       1: disable
     */
    UINT32 mask17 : 1;
    /* mask17 - Bits[17:17], RO, default = 1'b0 
       This register is a bit for bit mask for the CHANERR_INT register
       0: enable
       1: disable
       
       Notes:
       This bit is RO in functions 2-7
     */
    UINT32 mask18 : 1;
    /* mask18 - Bits[18:18], RO, default = 1'b0 
       This register is a bit for bit mask for the CHANERR_INT register
       0: enable
       1: disable
       
       Notes:
       This bit is RO in functions 2-7
     */
    UINT32 rsvd_19 : 13;
    /* rsvd_19 - Bits[31:19], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CHANERRMSK_INT_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* CHANERRSEV_INT_IIOCB_FUNC6_REG supported on:                               */
/*       IVT_EP (0x40026188)                                                  */
/*       IVT_EX (0x40026188)                                                  */
/*       HSX (0x40026188)                                                     */
/*       BDX (0x40026188)                                                     */
/* Register default value:              0x00000000                            */
#define CHANERRSEV_INT_IIOCB_FUNC6_REG 0x11064188
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x188
 */
typedef union {
  struct {
    UINT32 severity13_0 : 14;
    /* severity13_0 - Bits[13:0], RWS, default = 14'b00000000000000 
       1: Corresponding error logged in the CHANERR_INT register is escalated as fatal 
       error to the IIO internal core error logic. 
       0: That error is escalated as non-fatal to the IIO internal core error logic.
     */
    UINT32 chanerrsevro1_0 : 2;
    /* chanerrsevro1_0 - Bits[15:14], RO, default = 2'b00  */
    UINT32 severity16 : 1;
    /* severity16 - Bits[16:16], RWS, default = 1'b0 
       1: Corresponding error logged in the CHANERR_INT register is escalated as fatal 
       error to the IIO internal core error logic. 
       0: That error is escalated as non-fatal to the IIO internal core error logic.
     */
    UINT32 severity17 : 1;
    /* severity17 - Bits[17:17], RO, default = 1'b0 
       1: Corresponding error logged in the CHANERR_INT register is escalated as fatal 
       error to the IIO internal core error logic. 
       0: That error is escalated as non-fatal to the IIO internal core error logic.
       
       Notes:
       This bit is reserved for functions 2-7
     */
    UINT32 severity18 : 1;
    /* severity18 - Bits[18:18], RO, default = 1'b0 
       1: Corresponding error logged in the CHANERR_INT register is escalated as fatal 
       error to the IIO internal core error logic. 
       0: That error is escalated as non-fatal to the IIO internal core error logic.
       
       Notes:
       This bit is reserved for functions 2-7
     */
    UINT32 rsvd : 13;
    /* rsvd - Bits[31:19], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CHANERRSEV_INT_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


/* CHANERRPTR_IIOCB_FUNC6_REG supported on:                                   */
/*       IVT_EP (0x1002618C)                                                  */
/*       IVT_EX (0x1002618C)                                                  */
/*       HSX (0x1002618C)                                                     */
/*       BDX (0x1002618C)                                                     */
/* Register default value:              0x00                                  */
#define CHANERRPTR_IIOCB_FUNC6_REG 0x1106118C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.4.6.CFG.xml.
 * generated by critter 04_6_0x18c
 */
typedef union {
  struct {
    UINT8 dma_chan_err_pointer : 5;
    /* dma_chan_err_pointer - Bits[4:0], ROS_V, default = 5'b00000 
       Points to the first uncorrectable, unmasked error logged in the CHANERR_INT 
       register. This register is only valid when the corresponding error is unmasked 
       and its status bit is set and this register is rearmed to load again once the 
       error pointed to by this register, in the CHANERR_INT status register, is 
       cleared. 
     */
    UINT8 rsvd : 3;
    /* rsvd - Bits[7:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT8 Data;
} CHANERRPTR_IIOCB_FUNC6_STRUCT;
#endif /* ASM_INC */


#endif /* IIOCB_FUNC6_h */
